The present invention relates to chip carriers.
In conventional leadless chip-carriers, multiple layers of a ceramic (which usually is mostly alumina) are fired together to produce a structure having a cavity in which an integrated circuit chip can be mounted. The chip is connected to bond pads on a shelf inside the cavity, and a lid (e.g. of molybdenum or Kovar) is soldered on to make a hermetic seal on the cavity. Some of the ceramic layers which make up the chip carrier have metal traces patterned on them before firing, to make connections between the bond pads inside the hermetically sealed cavity and contacts on the outside of the chip carrier. Thus, the chip carrier can be mounted on a circuit board by making contact to its external contacts, while the chip remains hermetically isolated.
This technology is fairly mature and reliable, but some of its limitations must now be overcome. For example, at present there is a tremendous thrust towards finding ways to include multiple chips in a chip carrier. While it is possible to put more than one chip in the chip cavity and bond them out using conventional technology, this straightforward approach runs into several problems. One problem is footprint: putting four chips into a carrier should ideally require much less board area than four separate carriers would; but this advantage will not be fully obtained with prior art technology. Another problem is interconnect: the interconnect topologies permitted by the prior art chip carriers tend to be fairly simple, but optimal design of multi-chip modules would be greatly facilitated by more complex interconnect.
One way to achieve higher density per unit board area in multi-chip chip carriers would be to find some way to stack more than one layer of chips inside the carrier, but some way to make thermal and electrical connection to the upper layer of chips is necessary. Chips generate heat during operation, and in conventional technology much of this heat flows from the chips through the chip carrier's bottom surface (on which the chips are mounted) down through the circuit board, but this thermal path will not be available for all chips if more than one layer of chips is used. Thus, the problem of thermal dissipation is a major barrier to multi-chip packaging.
The present invention permits higher density in multi-chip carriers, by providing a chip carrier with improved packing density, wherein at least one layer of chips is bonded not directly to the substrate, but rather to a heat plate which attaches over the chip cavity and inside the hermetic sealing lid. The heat plate has openings in it to permit attachment of the leads from the chips in the upper layer to bond pads on a bonding ledge inside the cavity of the chip carrier, after the heat plate is emplaced. Each bonding ledge is preferably made somewhat wider than it would otherwise be, and the leads from multiple layers of chips are preferably bonded onto the same bonding ledge.
Thus, the present invention provides a multi-chip chip carrier where chips can be mounted in more than one layer, and the upper layer or layers of chips have good thermal connection to the circuit board.
The present invention also provides a multi-chip chip carrier with a very compact footprint.
The present invention also provides a new routing for interconnect between the chips and the external contact pads of a chip carrier, which permits interconnect topologies which would not otherwise be possible.
Another recent pressure on chip-carrier interconnect technology arises from the increasing use of processors having huge pinout numbers. For example, some kinds of symbolic processors or signal processors may require pinouts much greater than 100. This puts tremendous pressure on the interconnect capabilities of the conventional package. It may often be particularly advantageous to package such a high-pinout processor in close proximity to one or more other chips (cache memory, bus manager, coprocessor, etc.), but for such structures the conventional technology is totally inadequate. However, the present invention permits such configurations to be usefully exploited.
According to the present invention there is provided: A chip carrier comprising:
a chip carrier body having a cavity therein, and a lower mounting space, on the bottom of said cavity, for mounting at least one integrated circuit chip; PA0 at least one bonding ledge having contact pads thereon in proximity to said mounting space inside said cavity; PA0 a heat plate mounted above said lower mounting space within said cavity, PA0 at least one integrated circuit mounted on said lower mounting space, and at least one integrated circuit mounted on said second mounting surface; PA0 a plurality of connecting leads linking contact pads on said integrated circuits to selected contact pads on said bonding ledges; and PA0 a lid hermetically sealed to said body of said chip cavity, said lid and said chip cavity enclosing therebetween said lower mounting space, said heat plate, and said chips mounted thereon.
said heat plate being attached with low thermal resistance to said body of said chip carrier, said heat plate having a second mounting surface thereon for mounting at least one integrated circuit chip thereon;